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TABLE OF CONTENTS
1. GENERAL DESCRIPTION .......................................................................................................................1 2. FEATURES ...............................................................................................................................................1 3. ORDERING INFORMATION.....................................................................................................................1 5. FUNCTIONAL BLOCK DESCRIPTIONS ................................................................................................3 LCD Polarity Reverse Signal Generator...............................................................................................3 Clock Signal Generator .........................................................................................................................3 -V1 Discharge Circuit .............................................................................................................................3 Column Driver Voltage Generator ........................................................................................................3 Row Driver Voltage Generator ..............................................................................................................3 Row Driver Voltage Conversion Circuit ...............................................................................................3 VDD_ROW Voltage Generator...............................................................................................................3 +V1 Voltage Generator...........................................................................................................................3 6. PINS ASSIGNMENT .................................................................................................................................4 7. PIN DESCRIPTION ...................................................................................................................................5 8. DC CHARACTERISTICS ..........................................................................................................................8 Maximum Ratings...................................................................................................................................8 9. Electrical Characteristics ..................................................................................................................9 10. AC CHARACTERISTICS ......................................................................................................................10 Input Timing Characteristics...............................................................................................................10 Output Timing Characteristics............................................................................................................11 11. EXPLANATION OF FUNCTIONS.........................................................................................................12 LCD Polarity Reverse Signal Generator.............................................................................................13 Clock Signal Generator .......................................................................................................................14 Driver Voltage Generator.....................................................................................................................14
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Contrast Control Circuit ......................................................................................................................15 +V1 Voltage Generator.........................................................................................................................15 -V1 and +V1 Discharge Circuit ............................................................................................................16 Power Up and Power Down Sequence...............................................................................................16 12. APPLICATION CIRCUIT (SSD1730 5X STEP-UP MODE).................................................................17 13. PACKAGE DIMENSIONS.....................................................................................................................18
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SOLOMON SYSTECH LIMITED SEMICONDUCTOR TECHNICAL DATA
SSD1730
Advanced Infomation
SSD1730 MLA Power Chip CMOS
1. GENERAL DESCRIPTION
The SSD1730 is a power chip for operating four-line MLA (Multi Line Addressing) LCD drivers. It consists of a CMOS charge pump-type voltage converter that can generate all the bias voltages required for the four-line MLA drive based on a single power supply input. This can be used for the system that is formed by a column (segment) driver such as SSD1870 and a row (common) driver such as SSD1881. Such type of display system is able to produce a module with lower power consumption when comparing with the conventional driving method.
2. FEATURES
! Single Power Supply Operation, +2.4V to +3.6V
! ! ! ! ! ! ! ! Low current consumption Two step-up modes, 5X or 6X step-up by internal charge pump DC/DC converter Internal LCD voltage generator to generate all LCD voltages required for 4-line MLA driving External contrast control Internal -V1 discharge circuit to discharge the residual charge at the row driver negative voltage-side power supply voltage terminal -V1 Internal "power off" function using an external signal Equipped internally with a LCD polarity reverse signal generator Polarity reversed period in the range of 2P to 17P Available in 48 pin QFP package (0.5 mm terminal pitch)
!
3. ORDERING INFORMATION
Ordering Part Number SSD1730QL3 Package Dimension 7 mm x 7mm Package Form 48 LQFP
Table 1 - Ordering Information
This document contains information on a new product. Specifications and information herein are subject to change without notice. IC manufactured under Motif license including U.S. Patent No. 5,420,604 Copyright 2001 SOLOMON Systech Limited Rev 2.0 04/2002
4. BLOCK DIAGRAM
VDD_PWR VSS
L0 L1 L2 L3 FR XFR LCD Polarity Reverse Signal Generator Column (Segment) Driver Voltage Generator
C1P C1N C2P C2N -V3 C3P C3N V2 C4P C4N -V2
LP Clock Signal Generator Row (Common) Driver XSLP Voltage Generator C1PB C1NB -V3B HC
Row Driver Voltage Conversion Circuit
C5P C5N VEM C6N VEE
-V1 Discharge Circuit
VDD_ROW Voltage Generator
C8N VDD_ROW C7N
+V1 Voltage Generator
-V1 AB XBB
Figure 1 - Block Diagram
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5. FUNCTIONAL BLOCK DESCRIPTIONS
LCD Polarity Reverse Signal Generator
This circuit generates the polarity reverse signals FR and XFR from the pulse signal LP. The polarity reversal interval is controlled by four pins L0, L1, L2 & L3 and the range is from 2P to 17P (1P is equal to one LP period), Table 15 shows their relationship. The polarity of the FR signal and the XFR signal are mutually opposite, so that the upper and lower screens can be driven mutually in opposite phases when a two-screen drive panel is used.
Clock Signal Generator
This circuit generates the clock for the charge pump from the pulse signal LP. When the display control signal XSLP is set to VSS, the clock will stop and the voltage converter will halt. For normal display mode, XSLP must be tied to VDD_PWR. Besides, this circuit also generates the signals AB & XBB which are the clocks for the column driver voltage generator and the row driver voltage generator. Figure 7 shows their timing characteristics.
-V1 Discharge Circuit
When the display is off or the power is off, this circuit will discharge the residual charges at the negative voltage level-side power supply voltage terminal -V1 of the row driver.
Column Driver Voltage Generator
This circuit accompanying with external components generates voltages for column driver. In SSD1730, three voltage outputs including V2, -V2 and -V3 will be generated and their voltage levels are based on the supply voltage VDD_PWR. Their relationship is V2 = VDD_PWR/2, -V2 = -(VDD_PWR/2) and -V3 = -VDD_PWR.
Row Driver Voltage Generator
This voltage generator consists of three circuits (1) Row driver voltage conversion circuit, (2) VDD_ROW voltage generator and (3) +V1 voltage generator.
Row Driver Voltage Conversion Circuit
This circuit generates VEE voltage which is used to generate +V1 & -V1 power supply voltages for row driver. There are two step-up modes 5X and 6X which are set by the HC pin. When HC pin is tied to VSS, 5X step-up mode is chosen. When HC pin is tied to -V3B, 6X step-up mode is chosen. In SSD1730, VDD_PWR is taken as the reference, VEE is equal to -4 x VDD_PWR at 5X step-up mode while VEE is equal to -5 x VDD_PWR at 6X step-up mode. For the contrast adjustment, it is performed through the use of an external emitter follower circuit to adjust VEE to generate -V1, this contrast control circuit is shown in Figure 9.
VDD_ROW Voltage Generator
VDD_ROW voltage generator is used to generate VDD_ROW, which is the power supply to the logic circuit of a row driver.
+V1 Voltage Generator
+V1 voltage generator accompanies with an external MOS transistor to generate +V1 voltage, which is required for the row driver. Figure 10 shows the accompanying external circuit for generating +V1 voltage.
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6. PINS ASSIGNMENT
The package of SSD1730 is 48 LQFP and Table 2 shows its pin assignment.
Pin 1
Figure 2 - Pinout Diagram Pin# 1 2 3 4 5 6 7 8 9 10 11 12 Signal Name -V1 C8N VDD_ROW C7N VSS VEE C6N VEM C5N HC NC1 C5P Pin# 13 14 15 16 17 18 19 20 21 22 23 24 Signal Name -V3B C1NB VSS C1PB VDD_PWR C4N -V2 C4P -V3 VSS C1N C2N Pin# 25 26 27 28 29 30 31 32 33 34 35 36 Signal Name NC2 NC 3 -V3 C2P VDD_PWR C1P VSS C3N V2 NC4 C3P VDD_PWR Pin# 37 38 39 40 41 42 43 44 45 46 47 48 Signal Name L0 L1 L2 L3 VSS LP FR XFR XSLP XTST AB XBB
Table 2 - Pin Assignment Table
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7. PIN DESCRIPTION
Key: I =Input O =Output I/O = Bi-Directional (Input/Output) P = Power pin NC = Dummy pin Pin Name VDD_PWR VSS Type P P Pin# 17, 29 &36 5, 15, 22, 31 & 41 Description Power supply pin Ground pin
Table 3 - Power Supply Pins Pin Name L0 to L3 FR Type I O Pin# 37 to 40 43 Description These input pins are used to set the polarity reversal interval ranging from 2P to 17P. This is an output pin and the FR signal is generated from the LCD polarity reverse signal generator. This is an output pin and the XFR signal is also generated from the LCD polarity reverse signal generator. This signal is a reverse phase from FR signal.
XFR
O
44
Table 4 - Pins for frame signal generator Pin Name LP Type I Pin# 42 Description This input pin is used to generate the charge pump clock and the polarity reverse signal FR and XFR. A pulse signal with a period of 1P should be fed into this pin. This input pin is used to switch on or off the display. When it is set to VSS level, the clock and the operations of the voltage converter will be stop. The display will be off. When it is set to VDD_PWR level, the display will be on.
XSLP
I
45
Table 5 - Pins for clock signal generator
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Pin Name -V1
Type I/O
Pin# 1
Description This is the row driver negative voltage level power supply voltage terminal. The -V1 is an input signal to the contrast adjustment circuit this is used to adjust the display contrast. Besides, this is the power supply to the +V1 voltage generator control circuit.
Table 6 - Pins for -V1 discharge circuit Pin Name C1P Type I/O Pin# 30 Description The positive-side connection terminal for a capacitor C1 to generate -V3 output voltage. (Refer to the application circuit) The negative-side connection terminal for a capacitor C1 to generate -V3 output voltage. (Refer to the application circuit) The positive-side connection terminal for a capacitor C2 to generate -V3 output voltage. (Refer to the application circuit) The negative-side connection terminal for a capacitor C2 to generate -V3 output voltage. (Refer to the application circuit) This is -V3 output voltage, which is for the power supply of segment driver. The positive-side connection terminal for a capacitor C3 to generate V2 output voltage. (Refer to the application circuit) The negative-side connection terminal for a capacitor C3 to generate V2 output voltage. (Refer to the application circuit) This is V2 output voltage which is for the power supply of segment driver. The positive-side connection terminal for a capacitor C4 to generate -V2 output voltage. (Refer to the application circuit) The negative-side connection terminal for a capacitor C4 to generate -V2 output voltage. (Refer to the application circuit) This is -V2 output voltage which is for the power supply of segment driver.
C1N
I/O
23
C2P
I/O
28
C2N
I/O
24
-V3 C3P
O I/O
21, 27 35
C3N
I/O
32
V2 C4P
I/O I/O
33 20
C4N
I/O
18
-V2
O
19
Table 7 - Pins for column (segment) driver voltage generator
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Pin Name C8N
Type I/O
VDD_ROW
O
AB
O
XBB
O
C7N
I/O
C1PB
I/O
C1NB
I/O
-V3B HC
O I
C5P
I/O
C5N
I/O
VEM C6N
O I/O
VEE
O
Pin# Description Pins for VDD_ROW voltage generator 2 The negative-side connection terminal for a capacitor C11 to generate VDD_ROW output voltage. (Refer to the application circuit) 3 This is VDD_ROW output voltage which is the power supply to the logic circuit part of row driver. Pins for +V1 voltage generator 47 This is the clock output for the external n-channel MOS transistor control in the +V1 voltage generator circuit. 48 This is the clock output for the external p-channel MOS transistor control in the +V1 voltage generator circuit. 4 The negative-side connection terminal for a capacitor C18 to generate +V1 output voltage. (Refer to the application circuit) Pins for row driver voltage conversion circuit 16 The positive-side connection terminal for a capacitor C10 and C11 to generate -V3B output voltage. (Refer to the application circuit) 14 The negative-side connection terminal for a capacitor C10 to generate -V3B output voltage. (Refer to the application circuit) 13 This is -V3B output voltage equipped as the middle voltage level for generating VEE output voltage. 10 This pin is used to select 5X or 6X step-up mode. When it is tied to VSS, 5X step-up mode will be set. When it is tied to -V3B, 6X step-up mode will be set. 12 The positive-side connection terminal for a capacitor C8 and C9 to generate VEM output voltage. (Refer to the application circuit) 9 The negative-side connection terminal for a capacitor C8 to generate VEM output voltage. (Refer to the application circuit) 8 This is VEM output voltage equipped as the middle voltage level for generating VEE output voltage. 7 The negative-side connection terminal for a capacitor C9 to generate VEE output voltage. (Refer to the application circuit) 6 This is VEE output voltage.
Table 8 - Pins for row (common) driver voltage generator Pin Name XTST NC,1 NC2, NC3, NC4 Type I NC Pin# 46 11, 25, 26, 34 Description This is a test pin. This pin must be tied to the VDD_PWR level in normal application. Dummy Pins. These pins must be left open & unconnected in normal application.
Table 9 - Test circuit pins and Dummy pins
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8. DC CHARACTERISTICS
Maximum Ratings
Symbol VDD_PWR -V1 Vin IDD IV2 I-V2 I-V3 IVEE IVDD_ROW TA TSTG
Parameter Supply voltage Row driver negative supply voltage Input voltage Input current Output current at V2 Output current at -V2 Output current at -V3 Output current at VEE Output current at VDD_ROW Operating Temperature Storage Temperature Range Value 3.7 VEE-0.3 to 0.3 -0.3 to VDD_PWR+3.0 10 6 6 5 1 0.1 -20 to +85 -65 to +150 Unit V V V mA mA mA mA mA mA
C C
Table 10 - Maximum Ratings for DC characteristics (Voltage Referenced to VSS, TA=25C)
Maximum ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits shown in the Electrical characteristics table.
This device contain circuitry to protect the inputs against damage due to high static voltages of electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. All dummy pins and NC pins must be left open & unconnected. Do not connect or group dummy pins or NC pins together.
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9. Electrical Characteristics
Symbol Parameter Test Condition
(Absolute value referenced to VSS) (Absolute value referenced to VSS) VDD_PWR=2.4V to 3.6V, Display off (XSLP=VIL). VDD_PWR=2.7V, 5X step-up, LP period=69s, LP width=1s, Display on (XSLP=VIH), No loading VDD_PWR=2.7V, 6X step-up, LP period=69s, LP width=1s, Display on (XSLP=VIH), No loading 6X step-up, LP period=69s, LP width=1s, Display on (XSLP=VIH), Io=0.4mA (from VSS) 6X step-up, LP period=69s, LP width=1s, Display on (XSLP=VIH), Io=0.02mA (to - V1) VDD_PWR =2.7V VDD_PWR =2.4V
Min
2.4 VEE+0.6 --
Typ
3.3 -2
Max
3.6 -V3 5
Unit
V V A
VDD_PWR Supply voltage range -V1 Row driver negative supply voltage Range Standby Mode Supply Current Drain at VDD_PWR Display Mode Supply Current Drain at VDD_PWR in 5X step-up mode Display Mode Supply Current Drain at VDD_PWR in 6X step-up mode Output voltage at VEE pin
Istd
IDP1
--
270
380
A
IDP2
--
350
480
A
---
-12.25 -10.85 -V1+2.7 -V1+2.4 1.313 1.16 -1.276 -1.134 -2.646 -2.352
--
----------VDD_PWR
V V V V V V V V V V
VEE
Output voltage at VDD_ROW VDD_ROW pin
V2
-V2
-V3 VIH
VDD_PWR -=2.7V VDD_PWR -=2.4V VDD_PWR 6X step-up, LP period=69s, LP -=2.7V Output voltage at V2 pin width=1s, Display on VDD_PWR -(XSLP=VIH), Io=2mA (to VSS) =2.4V 6X step-up, LP period=69s, LP VDD_PWR -=2.7V width=1s, Display on Output voltage at -V2 pin (XSLP=VIH), Io=2mA (from VDD_PWR -VSS) =2.4V 6X step-up, LP period=69s, LP VDD_PWR -=2.7V width=1s, Display on Output voltage at -V3 pin (XSLP=VIH), Io=1mA (from VDD_PWR -VSS) =2.4V Input High voltage at pins: LP, XSLP, L0, L1, VDD_PWR = 2.4V - 3.6V 0.8*VDD_PWR L2, L3 and XTST Input Low voltage at pins : LP, XSLP, L0, L1, L2, L3 and XTST Output High Voltage at pins : XBB, AB, FR and VDD_PWR = 2.4V - 3.6V, Iout=-20A XFR Output Low Voltage at pins : XBB, AB, FR and XFR
0
V VIL
-0.2*VDD_PWR
VOH
VDD_PWR-0.1
--
VDD_PWR
V VOL VDD_PWR = 2.4V - 3.6V, Iout=-20A
0 -0.1
Table 11 - Electrical characteristics (Voltage Referenced to VSS, TA=25C)
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10. AC CHARACTERISTICS
Input Timing Characteristics
Symbol tLPC tLPW tLPr tLPf Parameter LP Period LP Width LP Rise Time LP Fall Time Min 50 70 --Typ 70 1000 --Max 125 *2000 10 10 Unit s ns ns ns
Table 12 - Input Timing Characteristics (Voltage Referenced to VSS, VDD_PWR = 2.4 to 3.6V, TA = 25C) Remark *: It is noted that the wider the positive LP pulse with, the higher the output impedance of the output voltage. The chip can function with positive LP pulse width in excess of 2000ns, but high output impedance will be found.
t L PW
LP
tL PC t LP r tL Pf
Figure 3 - Timing Characteristics for input pin LP
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Output Timing Characteristics
LP pulse width = 1000ns, -V1 = VEE + 0.6V, 6X step-up mode application Symbol tFRr tFRf tABr tAbf tXBBr tXBBf tOFFr tOFFf tC7Nr tC7Nf Parameter FR/XFR Signal Rise Delay Time (with loading = 50pF) FR/XFR Signal Fall Delay Time (with loading = 50pF) AB Signal Rise Delay Time AB Signal Fall Delay Time XBB Signal Rise Delay Time XBB Signal Fall Delay Time Rising Edge Output Phase Differential Time Falling Edge Output Phase Differential Time C7N Signal Rising Edge Delay Time C7N Signal Falling Edge Delay Time Min 330 330 230 180 130 280 1000 1000 270 490 Typ ----------Max 3300 3300 2000 1900 1100 3200 2400 2200 2400 3800 Unit ns ns ns ns ns ns ns ns ns ns
Table 13 - Output Timing Characteristics
tFRr tF Rf
FR XFR
LP
tABr tXBB r tABf
tXBBf
AB
tO F F r tOFFf
XBB
t C 7N f
tC 7N r
VSS VSS-1. 0V
tC7 Nf tC 7N r
VSS
C7N
VL+1.0V -V1+1.0V
VL
-V1
-V1
VL
Figure 4 - Output Timing Characteristics 11
SSD1730 Rev 2.0 04/2002 SOLOMON
11. EXPLANATION OF FUNCTIONS
This SSD1730 is a power chip for operating four-line MLA LCD drivers. It consists of a CMOS charge pump-type voltage generator which can produce all of the bias voltages for a four-line MLA driven. SSD1730 power chip can be used as a voltage generator to a display system formed by column driver such as SSD1870 and row driver such as SSD1881. In SSD1730, all output voltages are generated or reference from supply power VDD_PWR. The voltage levels at 5X or 6X step-up mode can be calculated by the logical formulas that are summarized in Table 14.
External components
+V1 +V1
VDD_PWR VSS
VDD_PWR V2 VSS -V2 -V3
V3 V2 VSS -V2 -V3
VC
SSD1870 Column Driver
VDD_ROW -V1 VEE VDD_ROW -V1
SSD1730 Power Chip
SSD1881 Row Driver
Figure 5 - Voltage levels relationship between power chip, column driver and row driver 5X Step-up Mode Voltage Level Logical Formula (VDD_PWR=3.3V) +V1=-(-V1) 13.2 - =4 x (VDD_PWR-VSS) - V3=VDD_PWR-VSS 3.3 V2=0.5 x (VDD_PWR-VSS) 1.65 VC=VSS 0.0 -V2=-0.5 x (VDD_PWR-VSS) -1.65 -V3=-V3B=-(VDD_PWR-VSS) -3.3 VEM=-2 x (VDD_PWR-VSS) -6.6 VDD_ROW=-3 x (VDD_PWR-9.9 + VSS) + -V1=-4 x (VDD_PWR-VSS) + -13.2 + VEE=-4 x (VDD_PWR-VSS) -13.2 6X Step-up Mode Voltage Level Logical Formula (VDD_PWR=3.3V) +V1=-(-V1) 16.5 - =5 x (VDD_PWR-VSS) - V3=VDD_PWR-VSS 3.3 V2=0.5 x (VDD_PWR-VSS) 1.65 VC=VSS 0.0 -V2=-0.5 x (VDD_PWR-VSS) -1.65 -V3=-V3B=-(VDD_PWR-VSS) -3.3 VEM=-3 x (VDD_PWR-VSS) -9.9 VDD_ROW=-4 x (VDD_PWR-13.2 + VSS) + -V1=-5 x (VDD_PWR-VSS) + -16.5 + VEE=-5 x (VDD_PWR-VSS) -16.5
Table 14 - Logical formula for SSD1730 (VSS = 0.0V)
Where is a variable and it must greater than or equal to 0 ( 0). In practice, it represents contrast adjustment value. SOLOMON Rev 2.0 04/2002 SSD1730
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LCD Polarity Reverse Signal Generator
This circuit generates the polarity reverse signals FR and XFR from the 1P period pulse signal LP. The polarity reversal period ranging from 2P to 17P is controlled by four pins L0, L1, L2 & L3. In such case, the upper and lower screens can be driven in mutually opposite phases when a two-screen drive panel is used, the polarity of the FR signal and the XFR signal are mutually opposite. The timing of the output transitions is synchronized with the falling edge of the LP signal. Figure 6 shows the timing diagram of LP, FR and XFR signals. Table 15 shows the relationship between the number of LP (NumLP) during the frame interval and the settings of L0 to L3.
XSLP
1P Pe riod
LP
FR XF R
N um LP
Num LP
Figure 6 - Timing Characteristics of LP, FR and XFR L0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 L1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 L2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 L3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Time 17P 2P 3P 4P 5P 6P 7P 8P 9P 10P 11P 12P 13P 14P 15P 16P Number Of LP (NumLP) th LP Signal 17 pulse nd LP Signal 2 pulse rd LP Signal 3 pulse th LP Signal 4 pulse th LP Signal 5 pulse th LP Signal 6 pulse th LP Signal 7 pulse th LP Signal 8 pulse th LP Signal 9 pulse th LP Signal 10 pulse th LP Signal 11 pulse th LP Signal 12 pulse th LP Signal 13 pulse th LP Signal 14 pulse th LP Signal 15 pulse th LP Signal 16 pulse
Table 15 - Relationship between NLP an L0 to L3
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Clock Signal Generator
This circuit generates the clock for charge pump circuit from the pulse signal LP. When the display off control signal XSLP is set to VSS, the clock will stop and the voltage converter will halt. The signal clocks AB and XBB for the column driver voltage generator and the row driver voltage generator are also generated by this circuit.
Input Signal XSLP
Input Signal LP
Output Signal AB
Output Signal XBB
Figure 7 - Timing diagram for LP, AB and XBB
Driver Voltage Generator
This circuit generates all voltage levels which are required to drive both the row driver and the column driver. The voltage converter circuit comprises a CMOS charge pump-type DC/DC converter which is formed by five individual voltage generator circuits including 1) Column driver voltage generator, 2) Row driver voltage conversion circuit, 3) VDD_ROW voltage generator circuit, 4) +V1 voltage generator circuit and 5) External contrast control circuit. Figure 8 shows the relationship between these voltage generator circuits and Table 14 summarized all logical formulas which can be used to calculated these voltage levels. Besides, in order to generate these voltages, external capacitors for the charge pump are necessary. Application circuit shows their connections
VDD_PWR Column driver voltage generator V3
VSS
V2 VC -V2 -V3
Row driver voltage generator -V3B Row driver voltage conversion circuit VDD_ROW voltage generator circuit VDD_ROW
VEM
+V1 voltage generator circuit
+V1
VEE
Ext. contrast control circuit
-V1
Figure 8 - Voltage generator control circuit
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Contrast Control Circuit
The display contrast level -V1 is controlled by an external contrast adjustment circuit. Figure 9 shows the typical connection of contrast control circuit.
-V3B 510k SSD1730A
VL -V1
VL -V1
500k
2SA
VEE
Figure 9 - Typical connection of contrast control circuit
+V1 Voltage Generator
This circuit generates voltage level +V1 which is the positive power supply to row driver. Signal AB and XBB are the clock for this generator circuit. Figure 10 shows the typical connection of the +V1 voltage generator.
3.3M 470pF
XBB SSD1730A
2SJ 1.0pF
+V1 VH
C7N
1.0uF
AB
2SJ
Figure 10 - Typical connection of +V1 voltage generator
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-V1 and +V1 Discharge Circuit
When XSLP is set to VSS level, the internal -V1 discharge circuit will be triggered and the residual charge at the row driver negative voltage-side power supply voltage terminal -V1 will be discharged to the VSS level. However, the residual charge at the row driver positive voltage-side power supply terminal +V1 can be discharged to the VSS level through an external MOS transistor. Figure 11 shows the typical connection of the +V1 discharge circuit.
VH +V1
SSD1730A
XSLP
3.3M 2SK 2SK
VSS
Figure 11 - Typical connection of +V1 discharge circuit
Power Up and Power Down Sequence
Proper power up sequence and power down sequence are recommended to protect the display system and to have better performance. Power Up Sequence: Start - Turn on the logic system in the application and power up the SSD1730 Display off - Set Column and Row Driver DOFF# to "L" Initialization - Send LP, YD, XSCL and Data # Stable - Wait for the power levels getting stable (around 80ms) Display on - Set Column and Row Driver DOFF# to "H" Power Down Sequence: Display off - Set Column and Row Driver DOFF# to "L" Sleep mode - Set power chip to sleep mode by setting XSLP to "L" # Discharge - Wait for the discharge of the display system (around 50ms) Power down - Cut the power of the SSD1730 End - Turn off the logic system of the application
#
Depends on the system loading.
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12. APPLICATION CIRCUIT (SSD1730 5X Step-Up Mode)
VDD=VDD_PW R
V3 FR XFR VDD C1P C1=4.7uF C1N FR XFR
VSS
VSS
C2P C2=4.7uF C2N C3P C3N C4P C4N C4=4.7uF C3=4.7uF
L3 L2 L1 L0 XTST
LP
LP
V2 VSS
V2 C5=4.7uF VC C6=4.7uF -V2 C7=4.7uF -V3 C8=1.0uF C9=1.0uF
XSLP
XSLP
-V2 -V3 C5N C5P C6N C1NB C1PB C8N HC -V3B VEM VDD_ROW -V1 C15=1.0uF VEE 3.3M C17=470pF XBB 2SJ C18=1.0uF C7N 2SK AB C19=1.0uF 2SK 3.3M 2SK 500k 2SA C16=1.0uF C13=1.0uF 510k C14=0.1uF C12=4.7uF
C10=4.7uF C11=0.1uF
VDD_ROW -V1
+V1
Figure 12 - Application Circuit for SSD1730 5X step-up mode
Remark: HC is tied to -V3B for 6X Step-up Mode. 17
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13. PACKAGE DIMENSIONS
9.00
7.00 Pin 1 Identifier 48
1
36
7.00
12
25
13 0.50 0.22 0.05
24
1.40.05
1.6max
9.00
0.25 min0.05 max0.15 0.6 0.15 1.00 48 LQFP (Dimension in mm, do not scale this drawing)
o 3.5 3.5
Figure 13 - Package Dimensions
SOLOMON
Rev 2.0 04/2002
SSD1730
18
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part.
19
SSD1730
Rev 2.0 04/2002
SOLOMON

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